Improving Memory Performance

Memory hierarchy considerations during sorting algorithm design and implementation play an important role in signiicantly improving execution performance. Existing algorithms mainly attempt to reduce capacity misses on direct-mapped caches. In order to further exploit cache locality to reduce other types of cache misses, we present several restructured mergesort and quicksort algorithms and their implementations by fully using existing processor hardware facilities, such as cache associativity and TLB, by integrating tiling and padding techniques, and by properly partitioning the data set. Our study shows that substantial performance improvement can be obtained by using our new methods. 1. INTRODUCTION Sorting operations are fundamental in many large scale scientiic and commercial applications. Sorting algorithms are highly sensitive to the memory hierarchy of the computer architecture on which the algorithms are executed, as well as sensitive to the types of data sets. Restructuring standard and algorithmically eecient sorting algorithms (such as mergesort and quicksort) to exploit cache locality is an eeective approach for improving performance on high-end systems. Such ex